|本期目录/Table of Contents|

[1]庞科,史再峰,周佳慧,等.基于FPGA的粗粒度可重构系统拓扑网络结构开发[J].天津大学学报(自然科学版),2018,(05):507-516.[doi:10.11784/tdxbz201705070]
 Pang Ke,Shi Zaifeng,Zhou Jiahui,et al.Network Topology Exploration of Coarse-Grained Reconfigurable Architecture Based on FPGA[J].Journal of Tianjin University,2018,(05):507-516.[doi:10.11784/tdxbz201705070]
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基于FPGA的粗粒度可重构系统拓扑网络结构开发()
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《天津大学学报(自然科学版)》[ISSN:0493-2137/CN:12-1127/N]

卷:
期数:
2018年05
页码:
507-516
栏目:
论文
出版日期:
2018-05-15

文章信息/Info

Title:
Network Topology Exploration of Coarse-Grained Reconfigurable Architecture Based on FPGA
文章编号:
0493-2137(2018)05-0507-10
作者:
庞科1 史再峰2 周佳慧2 陈可鑫2
1.天津大学计算机科学与技术学院,天津 30072; 2. 天津大学微电子学院,天津 300072
Author(s):
Pang Ke1 Shi Zaifeng 2 Zhou Jiahui2 Chen Kexin 2
1.School of Computer Science and Technology, Tianjin University, Tianjin 300072, China
2.School of Microelectronics, Tianjin University, Tianjin 300072, China
关键词:
粗粒度可重构系统硬件验证平台 拓扑开发流程 互连拓扑网络结构
Keywords:
coarse-grained reconfigurable architecture hardware emulation platform topology exploration flow network topology
分类号:
TN302.7
DOI:
10.11784/tdxbz201705070
文献标志码:
A
摘要:
针对粗粒度可重构系统架构的应用开发, 本文提出了一个基于FPGA的粗粒度可重构系统架构验证平台及相应的互连拓扑网络结构开发流程.基于FPGA开发板, 构建粗粒度可重构系统的验证模块及模块之间的拓扑互连被自动插入从而生成该系统架构的硬件验证平台.针对不同的应用, 该平台可以根据拓扑开发流程对不同拓扑互连策略下粗粒度可重构系统架构的性能和功耗进行评估分析.大量实验表明:CGRA的互连网络对该系统架构的性能和功耗有着巨大的影响, 最适宜的粗粒度可重构体系架构的互连策略取决于所选的拓扑结构.根据评估所获得的系统性能、功耗以及FPGA资源占用率, 设计者可以在较短的开发时间内准确地确定该应用最适宜的粗粒度可重构系统的拓扑互连策略.
Abstract:
With regard to the application development of coarse-grained reconfigurable architecture,a CGRA emulation platform based on FPGA and an exploration flow of network topology were presented in this paper. Based on FPGA,IP blocks(emulation blocks)and topology interconnection between IPs were inserted automatically to generate a CGRA hardware emulation platform. Following the exploration flow,the platform was used to evaluate timing performance and energy consumption of the CGRA with different topologies for different applications. The experiments demonstrate that the interconnection network of CGRA has a huge impact on timing performance and energy consumption,and the most appropriate interconnection strategy of CGRA strongly depends on the selected topology. Depending on the timing performance and energy consumption results obtained and the occupancy rate of FPGA resources,the designer can select the appropriate interconnection strategy of CGRA in a short exploration time and with precision.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期: 2017-05-26; 修回日期: 2017-11-02.
作者简介: 庞科(1978—), 女, 博士, pangke@tju.edu.cn.
通讯作者: 史再峰, shizaifeng@tju.edu.cn.
基金项目: 国家高技术研究发展计划(863计划)资助项目(2012AA012705); 国家自然科学基金资助项目(61674115).
Supported by the National High Technology Research and Development Program of China(No.,2012AA012705)and the National Natural Science Foundation of China(No.,61674115).
更新日期/Last Update: 2018-05-10