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 Pang Ke,Shi Zaifeng,Zhou Jiahui,et al.Network Topology Exploration of Coarse-Grained Reconfigurable Architecture Based on FPGA[J].Journal of Tianjin University,2018,(05):507-516.[doi:10.11784/tdxbz201705070]



[1] Cervero T, López S, Callicó G M, et al. Survey of reconfigurable architectures for multimedia applications [C]// Proceedings of SPIE, VLSI Circuits and Systems IV. Dresden, Germany, 2009:363-381.
[2] Dutta H, Kissler D, Hannig F, et al. A holistic approach for tightly coupled reconfigurable parallel processors[J]. Microprocessors & Microsystems, 2009, 33(1):53-62.
[3] Rossi D, Campi F, Spolzino S, et al. A heterogeneous digital signal processor for dynamically reconfigurable computing[J]. IEEE Journal of Solid-State Circuits, 2010, 45(8):1615-1626.
[4] Shan Gao, Kihara T, Shimizu S, et al. A novel traffic engineering method using on-chip diorama network on dynamically reconfigurable processor DAPDNA-2[C]// International Conference on High Performance Switching and Routing. Paris, France, 2009:1-6.
[5] Mei B, Sutter B D, Aa T V, et al. Implementation of a coarse-grained reconfigurable media processor for AVC decoder[J]. Journal of Signal Processing Systems for Signal Image & Video Technology, 2008, 51(3):225-243.
[6] Vahid F, Stitt G, Lysecky R. Warp processing:Dynamic translation of binaries to FPGA circuits[J]. Computer, 2008, 41(7):40-46.
[7] Singh H, Lee M H, Lu G, et al. MorphoSys:An integrated reconfigurable system for data-parallel and computation-intensive applications[J]. IEEE Transactions on Computers, 2000, 49(5):465-481.
[8] Atak O, Atalar A. BilRC:An execution triggered coarse grained reconfigurable architecture[J]. IEEE Transactions on Very Large Scale Integration(VLSI) Systems, 2013, 21(7):1285-1298.
[9] Ansaloni G, Bonzini P, Pozzi L. Heterogeneous coarse-grained processing elements:A template architecture for embedded processing acceleration[C]// Proceedings of the Conference on Design, Automation and Test in Europe. Nice, France, 2009:542-547.
[10] Marco L, Stefania P, Pasquale C, et al. A new reconfigurable coarse-grain architecture for multimedia applications[C]//2nd NASA/ESA Conference on Adaptive Hardware and Systems. Edinburgh, UK, 2007:119-126.
[11] Liang C, Huang X. SmartCell:A power-efficient reconfigurable architecture for data streaming applications [C]//IEEE Workshop on Signal Processing Systems. Washington, USA, 2008:257-262.
[12] Bouwens F, Berekovic M, Kanstein A, et al. Architectural exploration of the ADRES coarse-grained recon-
figurable array[C]//ARC2007:Reconfigurable Computing:Architectures, Tools and Applications. Mangaratiba, Brazil, 2007:1-13.
[13] Bouwens F, Berekovic M, de Sutter B, et al. Architecture enhancements for the ADRES coarse-grained reconfigurable array[C]//Proceedings of High Performance Embedded Architectures and Compilers, HiPEAC 2008. G?teborg, Sweden, 2008:66-81.
[14] Lambrechts A, Raghavan P, Jayapala M, et al. Energy-aware interconnect optimization for a coarse grained reconfigurable processor[C]//21st International Conference on VLSI Design. Hyderabad, India, 2008:201-207.
[15] Palkovic M, Hartmann M, Allam O, et al. Time-space energy consumption modeling of dynamic reconfigurable coarse-grain array processor datapath for wireless applications[C]//2010 IEEE Workshop on Signal Processing Systems(SIPS). San Francisco, CA, USA, 2010:134-139.
[16] Zain-ul-Abdin, Svensson B. Evolution in architectures and programming methodologies of coarse-grained reconfigurable computing[J]. Microprocessors & Microsystems, 2009, 33(3):161-178.
[17] Liu Yangfan, Liu Peng, Jiang Yingtao. Building a multi-FPGA-based emulation frame-work to support networks-on-chip design and verification[J]. International Journal of Electronics-INT J Electron, 2010, 97(10):1241-1262.
[18] Taylor M B. Is dark silicon useful?:Harnessing the four horsemen of the coming dark silicon apocalypse[C]// Proceeding 49th Design Automation Conference. San Francisco, CA, USA, 2012:1131-1136.


收稿日期: 2017-05-26; 修回日期: 2017-11-02.
作者简介: 庞科(1978—), 女, 博士, pangke@tju.edu.cn.
通讯作者: 史再峰, shizaifeng@tju.edu.cn.
基金项目: 国家高技术研究发展计划(863计划)资助项目(2012AA012705); 国家自然科学基金资助项目(61674115).
Supported by the National High Technology Research and Development Program of China(No.,2012AA012705)and the National Natural Science Foundation of China(No.,61674115).

更新日期/Last Update: 2018-05-10