|本期目录/Table of Contents|

[1]安胜彪,张琳,王保柱,等.一种基于分段电容的低功耗SAR ADC设计[J].天津大学学报(自然科学版),2017,(08):850-855.[doi:10.11784/tdxbz201604076]
 An Shengbiao,Zhang Lin,Wang Baozhu,et al.A Low Power SAR ADC Design Based on Segmented Capacitor[J].Journal of Tianjin University,2017,(08):850-855.[doi:10.11784/tdxbz201604076]
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一种基于分段电容的低功耗SAR ADC设计()
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《天津大学学报(自然科学版)》[ISSN:0493-2137/CN:12-1127/N]

卷:
期数:
2017年08
页码:
850-855
栏目:
电气自动化与信息工程
出版日期:
2017-08-31

文章信息/Info

Title:
A Low Power SAR ADC Design Based on Segmented Capacitor
文章编号:
0493-2137(2017)08-0850-06
作者:
安胜彪12 张琳2 王保柱2 王书海2 杨瑞霞1
1. 河北工业大学电子信息工程学院,天津 300401;2. 河北科技大学信息科学与工程学院,石家庄 050018
Author(s):
An Shengbiao12 Zhang Lin2 Wang Baozhu2 Wang Shuhai2 Yang Ruixia1
1.School of Electronic and Information Engineering, Hebei University of Technology, Tianjin 300401, China
2.School of Information Science and Engineering, Hebei University of Science and Technology, Shijiazhuang 050018, China
关键词:
逐次逼近型模数转换器 低功耗 失配校正 失调校正
Keywords:
successive approximation register analog-to-digital converter low power mismatch calibration offset calibration
分类号:
TK448.21
DOI:
10.11784/tdxbz201604076
文献标志码:
A
摘要:
针对当前物联网技术对功耗的严格要求, 设计了一种基于分段电容的低功耗SAR ADC电路.电路通过使用分离电容阵列来降低整个CDAC所需要的单位电容数和ADC的功耗.同时采用了分离电容校正技术来降低整体CDAC的非线性和失调校正技术来降低比较器电路的失调.在0.18 μm CMOS工艺下完成了一款10-bit 10-Msample/s的电路原型设计及相应的版图设计和验证工作, 带有PAD的芯片整体面积为1 .芯片后仿真结果表明:该转换器在校正情况下, 4.89 MHz输入信号频率下信号噪声谐波比(SFDR)为61.43 dB, 比不校正提高了54% ; 有效位数达到9.90 bit, 比不校正提高了3.7 bit; 在1.8 V电源电压下功耗仅为255.61 μW.
Abstract:
According to the strict requirements of the current networking technology on power consumption,a low power successive approximation register analog-to-digital converter(SAR ADC)circuit based on segmented capacitor has been designed. The capacitor array is used to reduce the number of unit capacity and power consumption of the ADC needed by the whole CDAC. At the same time,the separation capacitor calibration technique is adopted to reduce the overall CDAC nonlinear correction and the disorder technology is adopted to reduce the imbalance of the comparator circuit. A 10-bit 10-Msample/s circuit prototype design and the corresponding layout design and verification work have been completed under the 0.18 μm CMOS process,with PAD chip for the whole area is 1 mm2. The simulation results show that when the chip converter is under the condition of correction with 4.89 MHz input signal frequency,the spurious free dynamic range(SFDR)is 61.43 dB,which is 54% higher than without correction. The effective number of bits(ENOB) reached 9.9 bit,increased by 3.7 bit compared with that under the condition of non correction. The power consumption is only 255 μW at 1.8 V power supply.

参考文献/References:

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相似文献/References:

[1]赵毅强,耿俊峰,郑淑凤,等.一种基于开关逻辑结构的低功耗SAR ADC的设计[J].天津大学学报(自然科学版),2010,(10):879.
 ZHAO Yi-qiang,GENG Jun-feng,ZHENG Shu-feng,et al.A Low Power Successive Approximation Register Analog-to-Digital Converter Based on Switch Logic Architecture[J].Journal of Tianjin University,2010,(08):879.

备注/Memo

备注/Memo:
收稿日期: 2016-04-28; 修回日期: 2016-10-13.
作者简介: 安胜彪(1978—), 男, 副教授, anshengbiao@hebust.edu.cn.
通讯作者: 杨瑞霞, yangrx@hebut.edu.cn.
更新日期/Last Update: 2017-08-10