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[1]谢生,高谦,毛陆虹,等.2.5 Gb/s低噪声差分交叉耦合跨阻放大器的设计与实现[J].天津大学学报(自然科学版),2017,(06):656-660.[doi:10.11784/tdxbz201605045]
 Xie Sheng,Gao Qian,Mao Luhong,et al.A Novel 2.5 Gb/s Low Noise Differential Cross-Coupled Transimpedance Amplifier[J].Journal of Tianjin University,2017,(06):656-660.[doi:10.11784/tdxbz201605045]
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2.5 Gb/s低噪声差分交叉耦合跨阻放大器的设计与实现()
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《天津大学学报(自然科学版)》[ISSN:0493-2137/CN:12-1127/N]

卷:
期数:
2017年06
页码:
656-660
栏目:
微电子
出版日期:
2017-06-19

文章信息/Info

Title:
A Novel 2.5 Gb/s Low Noise Differential Cross-Coupled Transimpedance Amplifier
文章编号:
0493-2137(2017)06-0656-05
作者:
谢生 高谦 毛陆虹 吴思聪 谷由之
天津大学微电子学院,天津 300072
Author(s):
Xie Sheng Gao Qian Mao Luhong Wu Sicong Gu Youzhi
School of Microelectronics, Tianjin University, Tianjin 300072, China
关键词:
光接收机 调节型共源共栅 跨阻放大器 低噪声 CMOS
Keywords:
optical receiver regulated cascode configuration transimpedance amplifier low noise CMOS
分类号:
TN432
DOI:
10.11784/tdxbz201605045
文献标志码:
A
摘要:
本文基于UMC 0.18 μm CMOS工艺, 设计了一款低噪声交叉耦合结构的跨阻放大器.该电路由优化的调节型共源共栅(RGC)结构和输出缓冲级构成, 其中采用两级共源放大器作为RGC结构的辅助放大器, 用于提升电路的等效跨导和带宽.此外, 通过优化电路参数以及在输入端引入阶梯型无源匹配网络来进一步拓展带宽和降低电路噪声.测试结果表明, 在探测器等效电容为300 pF时, 所设计跨阻放大器芯片的-3 dB带宽为2.2 GHz, 跨阻增益为 61.8 dBΩ, 平均等效输入噪声电流谱密度仅为, 成功实现了2.5 Gb/s的传输速率.在1.8 V电源电压下, 芯片功耗为43 mW, 包括焊盘在内的芯片总面积为1×1 mm2
Abstract:
A low noise differential cross-coupled transimpedance amplifier(TIA)was designed and implemented in UMC 0.18 μm CMOS process,and the TIA consisted of a modified regulated cascode(RGC)configuration and an output buffer. An auxiliary amplifier constructed by two-stage common-source topology in RGC was adopted to improve the equivalent transconductance and the bandwidth. In addition,by optimizing the circuit parameters and introducing a ladder passive matching network at the input node,the bandwidth was further expanded and the noise was also reduced. The measured results demonstrate that the fabricated TIA with a photodetector capacitance of 300 pF has a transimpedance gain of 61.8 dBΩ and a -3 dB bandwidth of 2.2 GHz,and the average input-referred noise current spectral density is only . The eye pattern measurement shows that a data rate of 2.5 Gb/s is successfully achieved. The chip consumes 43 mW DC power under 1.8 V supply voltage and occupies an area of 1×1 mm2 including pads.

参考文献/References:

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备注/Memo

备注/Memo:
收稿日期: 2016-05-10; 修回日期: 2016-10-24.
作者简介: 谢生(1978—), 男, 博士, 副教授.
通讯作者: 谢生, xie_sheng06@tju.edu.cn.
基金项目: 国家自然科学基金资助项目(61474081).
Supported by the National Natural Science Foundation of China(No. 61474081).
更新日期/Last Update: 2017-06-10