|本期目录/Table of Contents|

[1]高静,杜增权,高天野,等.基于粗粒度可重构处理器的浮点乘加算法[J].天津大学学报(自然科学版),2017,(04):437-445.[doi:10.11784/tdxbz201601040]
 Gao Jing,Du Zengquan,Gao Tianye,et al.Floating-Point Multiplication and Addition Algorithm Based on Coarse-Grained Reconfigurable Processor[J].Journal of Tianjin University,2017,(04):437-445.[doi:10.11784/tdxbz201601040]
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基于粗粒度可重构处理器的浮点乘加算法()
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《天津大学学报(自然科学版)》[ISSN:0493-2137/CN:12-1127/N]

卷:
期数:
2017年04
页码:
437-445
栏目:
微电子
出版日期:
2017-04-30

文章信息/Info

Title:
Floating-Point Multiplication and Addition Algorithm Based on Coarse-Grained Reconfigurable Processor
作者:
高静1 杜增权1 高天野1 罗韬2 史再峰1
1. 天津大学微电子学院,天津 300072;2. 天津大学计算机学院,天津 300072
Author(s):
Gao Jing1 Du Zengquan1 Gao Tianye1 Luo Tao2 Shi Zaifeng1
1. School of Microelectronics, Tianjin University, Tianjin 300072, China
2. School of Computer Science and Technology, Tianjin University, Tianjin 300072, China
关键词:
可重构处理器 粗粒度 浮点运算
Keywords:
reconfigurable processor coarse-grained floating-point operations
分类号:
TN492
DOI:
10.11784/tdxbz201601040
文献标志码:
A
摘要:
在粗粒度可重构处理器中, 往往采用以定点代替浮点或嵌入专用的浮点计算单元的方式来处理应用中的浮点运算, 从而导致在面对大动态范围运算时精度不够, 造成系统面积与功耗的增加.本文提出了一种在通用粗粒度可重构处理器上用定点运算单元实现浮点乘加运算的方法, 采用8个可重构处理单元实现1次乘或加的浮点运算, 该方法不仅兼容了IEEE-754的单精度浮点标准而且没有增加任何浮点运算硬件.在模拟器上对系统性能进行测试, 使用本文的方法, 在通用粗粒度可重构处理器上实现浮点乘法运算性能提升2.09倍, 浮点加法运算性能提升1.68倍.
Abstract:
For coarse-grained reconfigurable processors,there are two approaches to dealing with floating-point operations. The first one is using fixed-point operations instead of floating-point,and the second one is embedding a floating-point calculation unit. But both the two methods will cause low accuracy in large dynamic range calculation,and increase the system area and power consumption. This paper presents a method of floating-point multiplication and addition implemented on a general coarse-grained reconfigurable processor with fixed-point arithmetic units by using eight reconfigurable processing units to implement a floating-point multiplication or addition operation. The method is compatible with the IEEE-754 single precision floating point standard but does not add any floating-point arithmetic hardware. The performance of the system is evaluated by SOC designer. The results show that the performance of floating-point multiplication operation improves 2.09 times,and addition operation improves 1.68 times compared with the conventional one on the general coarse-grained reconfigurable processor architecture.

参考文献/References:

[1] Hartenstein R. A decade of reconfigurable computing:A visionary retrospective [C]// Proceedings of the Conference on Design, Automation and Test in Europe. Munich, Germany, 2001:642-649.
[2] Compton L, Hanks S. Reconfigurable computing:A survey of systems and software[J]. ACM Computing Surveys, 2002, 34(2):171-210.
[3] Singh H, Lee M H, Lu G M, et al. MorphoSys:An integrated reconfigurable system for data-parallel and computation-intensive applications[J]. IEEE Transaction on Computers, 2000, 49(5):465-481.
[4] 姚于斌. 面向图像处理的可重构处理器结构设计研究[D]. 上海:上海交通大学微电子学院, 2008.
Yao Yubin. Research and Design on Reconfigurable Coprocessor Architecture for Image-Processing Application [D]. Shanghai:School of Microelectronics, Shanghai Jiaotong University, 2008(in Chinese).
[5] Yiannacouras P, Steffen J G, Rose J. Portable, flexible, and scalable soft vector processors[J]. IEEE Transaction on Very Large Scale Integration(VLSI) Systems, 2012, 20(8):1429-1442.
[6] Dou Y, Lu Y C. LEAP:A data driven loop engine on the array processor [C]//International Workshop on Advanced Parrallel Processing Technology. Xiamen, China, 2003:12-22.
[7] Beauchamp M J, Hauck S, Underwood K D, et al. Architectural modifications to enhance the float-point performance of FPGAs [J]. IEEE Transactions on Very Large Scale Integration System, 2008, 16(1):177-187.
[8] Ho C H, Yu C W, Leong P, et al. Floating-point FPGA:Architecture and modeling[J]. IEEE Transactions on Very Large Scale Integration Systems, 2009, 17(12):1709-1718.
[9] Jo M, Arava V K P, Yang H, et al. Implementation of floating-point operations for 3D graphics on a coarse-grained reconfigurable architecture[C]// Proceedings of the 20th IEEE International SOC Conference. Hsin Chu, Taiwan, China, 2007:127-130.
[10] Jo M, Lee D, Choi K. Chip implementation of a coarse-grained reconfigurable architecture supporting floating-point operations [C]// Proceedings of the 5th International SOC Design Conference. Busan, South Korea, 2008:29-30.
[11] Lee D, Jo M, Han K, et al. FloRA:coarse-grained reconfigurable architecture with floating-point operation
capability[C]//Proceedings of the 2009 International Conference on Field-Programmable Technology. Sydney, Australia, 2009:376-379.
[12] Jo M, Lee D, Han K, et al. Design of a coarse-grained
reconfigurable architecture with floating-point support and comparative study[J]. Integration the VLSI Journal, 2013, 47(2):232-241.
[13] IEEE. Floating-Point Arithmetic [S]. New York:IEEE, 2008.
[14] Brunelli C, Garzia F, Rossi D, et al. A coarse-grain reconfigurable architecture for multimedia applications supporting subword and floating-point calculations[J]. Journal of Systems Architecture, 2010, 56(1):38-47.
[15] Brunelli C, Garzia F, Nurmi J. A coarse-grain reconfig-urable architecture for multimedia applications featuring subword computation capabilities [J]. Journal of Real-Time Image, 2008, 3(1/2):21-32.
[16] Brunelli C, Cinelli F, Rossi D, et al. A VHDL model and implementation of a coarse-grain reconfigurable coprocessor for a RISC core [C]//Research in Microelectronics and Electronics. Otranto, Italia, 2006:229-232.

备注/Memo

备注/Memo:
收稿日期: 2016-01-11; 修回日期: 2016-05-25.
作者简介: 高静(1979—), 女, 博士, 副教授, gaojing@tju.edu.cn.
通讯作者: 史再峰, shizaifeng@tju.edu.cn.
基金项目: 国家高技术研究发展计划(863计划)资助项目(2012AA012705); 国家自然科学基金资助项目(61404090, 61306070); 天津市科技支撑计划资助项目(14ZCZDGX00034).
Supported by the National High Technology Research and Development Program of China(No. 2012AA012705), the National Natural Science Foundation of China(No. 61404090, 61306070) and the Science and Technology Support Program of Tianjin, China (No.,14ZCZDGX00034).
更新日期/Last Update: 2017-04-10